The hardware description languages (HDL) used in chip development are like programming languages. The existing models understand them and can do a lot with them. You don’t need to have separate, specialty models designed for this work to use LLMs in chip design workflows.
Design verification also involves a lot of traditional programming which benefits from LLMs.
So it’s not meaningless at all. You could download some of the open source chip design software today and the LLMs could even help you get started on your own tiny chip if you are so interested.
I tried making a button using Claude entirely (including the 3D printed enclosure) and it effed up pretty hard with the traces and the header spacing. The project was a big red arcade button that plays the "ah-my-groin.mp3" when pushed (from Simpsons). It did cool work on saving battery life, and the 3d enclosure was awesome, but yeah, I'm convinced I'd have to do another version or two of the custom chip until it came back right. I used a Blender MCP for the 3d modeling. I used a KiCAD MCP server for the chip design/validation.
I think we're not there yet. I've been meaning to look at this flux.ai to see if it has the prompts/workflow worked out better than what I was able to cobble together in a few hours. Maybe Alteryx's MCP server would have been better. I'll try that this weekend for another board I've got.
> I tried making a button using Claude entirely (including the 3D printed enclosure) and it effed up pretty hard with the traces and the header spacing.
PCB design and 3D CAD design are different topics.
Hardware Description Languages are closer to programming languages than CAD. Look at some Verilog to get an idea - https://en.wikipedia.org/wiki/Verilog
Right. KiCAD for PCB design. Blender for 3D CAD. Oh, are you saying I should have used something other than the KiCAD MCP server for better results?
Designing circuit board and 3D models (even using something like OpenSCAD) is a very spatial process today. You are dealing with coordinates one way or another.
This is very unlike how FPGA and (I assume) ASIC is done. That is more like a traditional programming language but everything happens all at once (no sequence of statements outside tests, if you need that you have to write a state machine yourself). You define logic expressions between signal, add stateful latches, etc. But you never specify the physical layout.
Instead you feed your description to a tool that acts a constraint solver/optimiser that computes the layout for you (this is for FPGAs called synthesising IIRC, it is akin to a compiler). Typically quite slow, even for small circuts like we did at university it took minutes, and for large circuits it might easily days.
Now, this raises the question, what if you design a PCB net list using AI, but then use traditional autorouting and layout? I believe that can also be done, but I have no experience designing PCBs, so I don't know how well it works.
Autorouting PCBs doesn’t really give usable results on all but the simplest cases. It seems to be a very difficult problem to solve even though a human doing it is only following a relatively simple bunch of rules and goals in his or her head.
Simple bunch of rules and goals backed by extremely sophisticated visual intuition.
Pretty sure someone already tried throwing VLMs and diffusion models at this, wonder how that fared.
VHDL is not a language for spatial design. Its more akin to a programming language with circuit semantics.
For digital chip design, research Verilog and/or SystemVerilog, and for tools, check out verilator and the OSS cad suite: https://github.com/YosysHQ/oss-cad-suite-build
They’re saying that VHDL is an entirely different concept than physical modeling.
You're comparing apples and oranges.
Meta: can we not downvote people who are clarifying what they're saying and asking questions, even if they're wrong about something, if the content isn't otherwise objectionable?
I didn’t downvote, but the OP is either a troll or someone who doesn’t want to notice he doesn’t know what he’s talking about. Either way we want less of that on HN.
I'll acknowledge that I don't know what I'm talking about. I really appreciated the clarity! Surely you find value in knowing that creating your own custom chips is almost doable by someone who doesn't know what they're talking about! (also, I am a troll, but in this case, just clueless)
Maybe the confusion stems from the word "chip". Creating a chip usually means designing and producing a microcontroller or a processor, not a printed circuit board that you populate with existing chips.
Ohhhhhh! Yes, that's exactly the problem. It all makes sense now. I was just piecing together an existing microcontroller and a mp3 module by printing a custom circuit board.
One (kicad) make the board, the other (blender) make the casing for it. Both are “hardware” but is electronics and the other is mechanical. Electronic one AI can do a good job, I can’t wait for it to fully built the whole circuit for you based on your specs.
PCB layout is an art, and doesn't seem to map well to LLMs (I tried for shits and giggles recently). Claude in general, kind of like code, does a lot of redundant belt and suspenders stuff in the schematics it generates (if it can generate them at all). It's one of those things that's really not there yet outside of the simplest designs.
DeepPCB has an AI autorouter [1] that uses reinforcment learning and works really well. Recently they also released an AI agent that analyzes your board, proposes plans and can route your board for you [2]. They have a KiCad plugin [3] and you can try it for free.
[1] https://deeppcb.ai/reinforcement-learning-pcb-routing-explai... [2] https://deeppcb.ai/cooper/ [3] https://deeppcb.ai/deeppcb-kicad-plugin-ai-pcb-routing/
Disclaimer: I work at InstaDeep, the company behind DeepPCB, but I don't work on this product.
Sounds like a super cool project. Gonna post the design anywhere?
I'll update it this weekend with the updated AI-generated fun (and correct the flat-out ai-generated lies in the README). Meanwhile, you can see the project here. https://github.com/knicholes/ah-my-groin-button
The question isn’t whether or not they employed a particular tool, the question is how big of an impact did it have.
Most HDL code is locked up behind corporate firewalls and not available as training data. While LLMs can handle it to an extent there's a lot of room for improvement. I'll bet that OpenAI and their competitors are racing to license this IP from major hardware vendors in order to compete in the chip design vertical.
Does it work better when using compiler based ecosystem (e.g. https://github.com/llvm/circt)
There is quite a lot of Verilog/SystemVerilog and VHDL code in the wild. And hardware description language code is very simple and straightforward relative to programming code.
And the two things that take up VAST amounts of time in ASIC design are testbenches and timing closure.
A LOT of hardware design is testbenches to verify things. AI is REALLY GOOD at generating things like testbenches. And nobody really cares if the quality of your testbench code sucks as long as it validates what it claims to.
I don't know how good AI is at timing closure, but I wouldn't necessarily be surprised if it is pretty good at it up to the physical point. That's lots of textual output which you can put a constraint on.
Everything involving physical design, though, tends to be a disaster waiting to happen if you let AI loose on it.
This reminds me of the dude on youtube building a chip fab in his shed.
> The existing models understand them
No they don't.
One day we can design our own pcb with chips, hardware and other io. Companies will accept these as files and you can collect your pcb the same day. I think in China they are doing this already
hasn't pcbway been doing this for years?
> The existing models understand them and can do a lot with them.
In my experience they are not especially good at SystemVerilog. There's a lot of knowledge about it that is locked behind paywalls and it's very niche.
My guess is the "from scratch" here is quite the exaggeration. Otherwise why did they need Broadcom?
Doesn’t Broadcom bring a lot more to bear here than just Verilog? Including relationships with the actual fabricators.
I doubt that is really significant - fabs are happy to work with anybody. What they will likely bring is:
* Physical design team (stupidly known as the "backend"). This is extremely specialised knowledge and most chip companies don't really want to have to deal with it if they can avoid it.
* IP blocks. Especially for annoying things like phys, memory controllers, USB controllers, PLLs, power, etc. These things are difficult to do, difficult to test, and often critical (good luck if your clock doesn't work...) I would not at all be surprised if Broadcom supplied CPUs too.
My total guess at what happened is Broadcom supplied most of a SoC and OpenAI added an LLM coprocessor module to it, and probably asked them to add like 10x more DRAM interfaces.
Not having a free toolchain that can actually handle the real language has probably been pretty bad on the downstream public knowledgebase. Hopefully Verilator can eventually close that hole, and there can be more high-quality designs and codebases incorporated into future models. Claude is at least good enough to write SV that triggered a compiler crash or two. :)
Broadcom also has direct allocation with TSMC, which is a big win