For digital chip design, research Verilog and/or SystemVerilog, and for tools, check out verilator and the OSS cad suite: https://github.com/YosysHQ/oss-cad-suite-build
For digital chip design, research Verilog and/or SystemVerilog, and for tools, check out verilator and the OSS cad suite: https://github.com/YosysHQ/oss-cad-suite-build