righto.com has been great reading. None of my friends wanted to pay for an 8087, but I can still remember getting out of school (for 2nd time) and saving up for the 486DX after 3 others got them. After that, well, it's been quite a ride.
There's a ton of coordination lately on P6 microcode. Would love to see what twists and turns there are supporting the older isa on newer architectures
That instruction was only introduced with the 80287. Unlike the 8086/8088, the 286 CPU was aware of different classes of x87 opcodes: it had to distinguish between ones that read or write memory, and some special control instructions as well.
So FSTSW AX was handled by the CPU microcode, which would read the status word from a reserved I/O port and put it into AX.
The 386 was even more tightly integrated, with some of the FPU state duplicated inside the CPU, so that it could store it to memory in different formats depending on whether it was currently in 16- or 32-bit mode.
righto.com has been great reading. None of my friends wanted to pay for an 8087, but I can still remember getting out of school (for 2nd time) and saving up for the 486DX after 3 others got them. After that, well, it's been quite a ride.
Minor erratum: "1.1 (binary) × 2^8 is 304" should be 384.
Thanks! I guess I didn't have my glasses on when I read that number :-)
If your look at {whatever part is next} is this interesting, I don't know if "which one?" really matters much.
There's a ton of coordination lately on P6 microcode. Would love to see what twists and turns there are supporting the older isa on newer architectures
Have you already covered how the decoding of instructions is shared with the 8086?
I describe the 8087 instruction decoding here: https://www.righto.com/2026/02/8087-instruction-decoding.htm...
How do FSTSW AX and similar instructions write to AX?
That instruction was only introduced with the 80287. Unlike the 8086/8088, the 286 CPU was aware of different classes of x87 opcodes: it had to distinguish between ones that read or write memory, and some special control instructions as well.
So FSTSW AX was handled by the CPU microcode, which would read the status word from a reserved I/O port and put it into AX.
The 386 was even more tightly integrated, with some of the FPU state duplicated inside the CPU, so that it could store it to memory in different formats depending on whether it was currently in 16- or 32-bit mode.
I am curious about the transcendental instructions, how are they implemented, and used, and if actually used
https://www.righto.com/2026/09/8087-tangent-cordic.html
They definitely were used back in the day, now the x87 isn't used much at all.