What's wild is that the mirrors used in the EUV machines are smooth to a level of deviation even smaller that the feature size of the gates being etched.
These mirrors are up to a couple of feet in diameter, with an average smoothness deviation of less than the width of an atom, maximum bump size of 1nm or less. They like to point out that if scaled up to the size of Germany (Zeiss makes them), the biggest surface defect would still only be 0.1mm!
I did find it funny recently when Huawei when talking about its folded logic say the Vertical Bonding Pitch's are every 15,000 angstroms. It is a very fancy way of saying an interconnect every 1.5 microns.
What's wild is that the mirrors used in the EUV machines are smooth to a level of deviation even smaller that the feature size of the gates being etched.
These mirrors are up to a couple of feet in diameter, with an average smoothness deviation of less than the width of an atom, maximum bump size of 1nm or less. They like to point out that if scaled up to the size of Germany (Zeiss makes them), the biggest surface defect would still only be 0.1mm!
I did find it funny recently when Huawei when talking about its folded logic say the Vertical Bonding Pitch's are every 15,000 angstroms. It is a very fancy way of saying an interconnect every 1.5 microns.
They should just say every 7 silicon atoms at that point.
7500 surely? But yeah at this point I feel like the diameter of a silicon atom would make for a better unit of measure.
Oh right i was thinking the feature size (about that many namometers not microns)