In simpler terms, the SRAM density improved by 2.9% (according to ChatGPT). Which is better than it sounds, because SRAM had reached a wall, in terms of density gains, and, chips can be dominated by SRAM in terms of surface area, so this can mean a lot more room for logic, even though that is also getting considerably denser.
There's some hope of smaller SRAM in the future - https://raaam-tech.com/technology/ is a three-transistor SRAM.
It's not quite SRAM, it needs to be refreshed like DRAM. That's the main downside compared to SRAM but it's still very interesting.
Yes, the density vs power tradeoff could make a lot of sense in a few applications.
I wonder if it would start to make sense for SRAM caches to shrink (or not grow as fast) in favor of adding on chip DRAM cache at some tier.
Or AMD’s putting sram on a separate chip. I’m surprised they didn’t go there yet except for extra L3 instead of all of it. At some point the costs will shift the decisions.
They claim win + win*10:
> provides up-to 50% area reduction and reduced power consumption by a factor ten
This is exactly why Cerebras wafer chips aren’t even on N3. They stayed on N5. It is also why they are now stacking HBM onto the chip.