> RISC-V is now officially supported by CPython as a tier 3 platform!
That's significant, but tier 3 is still a caveat. Still allowed to break without blocking anything or being fixed as a priority.
> RISC-V is now officially supported by CPython as a tier 3 platform!
That's significant, but tier 3 is still a caveat. Still allowed to break without blocking anything or being fixed as a priority.
Sure, but I had to look:
Tier1: Windows x64/i686, Linux x64/ARM gcc, Darwin/ARM
Tier2: Linux x64/ARM w/ clang, Windows ARM, WASM, Darwin/x64
Tier3 is a pretty low support level, but tiers 1 and 2 is a pretty short list of major commercial platforms. Also even for developers to fix, availability of e.g. RiscV machines in the cloud to reproduce and fix on is still somewhat limited.
Windows i686, tier 1, what? I’ll do some digging when I’m home but I feel the sudden need to understand this.
Oh, wow
https://learn.microsoft.com/en-us/lifecycle/products/windows...
Interestingly embedded 32 bit Linux is not tier 1 or 2 though :)
Needs to start somewhere.
Looks like the most important step towards tier two is mostly about proving the CI infrastructure is reliable (which takes time at tier 3), and have at least two core developers committed to fixing any issues (within 24 hours)
Atleast CI-class hardware finally exists, with the sifive bigsky
https://www.sifive.com/development-platforms/sifive-bigsky-s...
RISC-V is one of those experimental architectures that hardly anyone is actually using, isn't it?
Tier 3, or no support at all, seems an appropriate designation.
Not much on user facing OS, but billions of small controllers
I don't think CPython targets those, though; that seems more like a micropython thing?