> The fact that the relevant CPU features can’t even be enumerated in user mode just makes it worse.

User-mode feature detection is usually used to select paths for acceleration instructions, like SIMD or crypto. The overlapping RISC-V instructions don't fit in that category: they're compressed versions of basic functions, mostly used in epilogs/prologs, which would be unconditionally compiled in.

There are no overlapping encodings in the 32-bit encoding space and I'm really hoping it stays that way.

> To the extent that there are lessons to be learned, RISC-V should have learned them.

Yeah, I think I agree with this. Also I wish I had been there when Andrew Waterman was writing his master's thesis so I could ask him not to include Whetstone in his size benchmarks, so that we might have left that encoding space free and avoided this conversation :-)