In general, more complex processors have latency issues, and in some ways modern chips have actually become worse with each design iteration.

https://en.wikipedia.org/wiki/Metastability_(electronics)

Ultimately... failure modes must arise because naive gate design simulation models can't determine issues in a computationally feasible time frame.

The consequences of "fixing" CDC prone design flaws makes a processor many times slower (8 to 16 times slower on my dumb attempt), and develops weird alien design features very different from Von Neumann architectures.

This is why we can't have nice things. =3