I'm more thinking about how MIPS were quite late to branch predictors.

They were shipping the high-performance R4000 and R4400 with 8 stage pipelines and no branch predictors.

They could have really done with a branch predictor, each branch took three cycles (and the branch delay slot could fill only one instruction, often a useless NOP).

The Pentium only had a 5 stage pipeline and massively benefited from its branch predictor. IBM was slapping branch predictors on PowerPC designs with 4 stage integer pipelines. You simply don't need a long pipeline to justify the benefits of a branch predictor.