What is interesting here is that this is an optimization study, whose goal was to determine the optimum implementation variant for matrix multiplication on a Zen 3 CPU.

It is likely that a similar optimization strategy would work for a modern Zen 5, though some of the parameters for the optimum variant would probably have double values, because Zen 5 has twice more registers, each double in size, and it can process and transfer a double number of FP32 per clock cycle.

The value given by the author of 63.5% of the theoretical maximum throughput, is likely to be pessimistic, because when doing heavy computations the clock frequency of the CPU will drop, so the actual efficiency might be higher, e.g. perhaps of 70% to 80% of the theoretical maximum throughput at that clock frequency.

The ATLAS BLAS-compatible library attempted to perform automatically such an optimization for its host computer, but I have not studied it to see whether its optimization methods would still work on modern CPUs with AVX+FMA or with AVX-512.