Zen3 isn't the best performing CPU today, though of course it'll never approach GPU level (which is pretty much ASIC level for matrix muls with special units). CPUs are getting dedicated "AI accelerators" too so it'd be interesting to compare per watt. The real limit is almost certainly memory bandwidth, not flops.
It would also be very interesting to see someone like Fabien Giesen / ryg do a maxed out AVX512 version for Zen5. His code's so fast it makes Intel 13900k's self destruct.
Matrix multiplication is one of the few operations that isn't regularly limited by memory bandwidth. BLAS implementations come with several heavily optimized, architecture-specific versions of sgemm.
Well, it does rely on decomposing the problem to optimize cache efficiency.
I don't read Portuguese, but the tables of results seem to imply they are tuning block sizes that leverage the L3 cache. They also talk about prefetch, which tends to matter more as you are approaching a streaming pattern.
So, a single core result may not scale linearly for multicore, given that there will be some cache contention, right? It's a very different tuning problem to optimize each of N cores to use its 1/N fraction of cache while sharing the available bandwidth for cache misses.