The field is moving too fast for it to make sense. ASICs have a 12-24 month development cycle and you’d have to throw them in the trash 4 months later.
The field is moving too fast for it to make sense. ASICs have a 12-24 month development cycle and you’d have to throw them in the trash 4 months later.
If this approach doesn't include a way to apply updated finetunes on a daily basis (also without going back to VRAM being the bottleneck) then the trash interval would be measured in hours, not months