For anyone who needs it, a friendly reminder that CPU nm marketing is a complete fabrication and the physical size of transistors has zero relation to the marketing claims. These are not, in fact, physically sub 1 nm, despite the bombastic claims.
For anyone who needs it, a friendly reminder that CPU nm marketing is a complete fabrication and the physical size of transistors has zero relation to the marketing claims. These are not, in fact, physically sub 1 nm, despite the bombastic claims.
>These are not, in fact, physically sub 1 nm, despite the bombastic claims.
Why? What's their real size?
Not doubting you, just trying to understand and also trying to assess how exaggerated the marketing is.
At some point in the transistor scaling, the electrons started leaking across the gate, we've switched from 2D design to 3D structures to prevent that, so the actual physical gate pitch for like the TSMC 3nm is around 45 nm in distance.
Currently thrown around numbers mean the "equivalent performance/density" or something like that.
They don't describe the exact physical size (that would rather defeat the point of the marketing), but you can see the photographs at the bottom have a scale measured in tens of nm.
The marketing nm better represent the density and performance of the transistors than the actual feature size, especially in this case.
So the title should be corrected. The did not debut sub nm chips at all.
That ship sailed long ago. I think it was around 32nm-22nm node when the marketing term started diverging from the physical feature size.
More reason to frame it correctly, like "IBM debuts another 5 nanometer chip technology, selling it as sub nanometer chip technology"