This is also very well documented. Probably as part of the assessment, but it's nice to see.
It doesn't appear to have any kind of interrupts, which is quite a limitation for actual usecases, but also makes the architecture much simpler.
The use of dual phase clocking is interesting. The document describes it as having the control and data paths operating on opposite phases. I'm curious as to where you got this technique from, since it's not common (apart from the use of both edges by DDR RAM). I also suspect that it would go away if you had better tooling for managing setup and hold violations (does logisim do that for you, or did you have to manage it manually somehow?). Not all FPGA tools like nonstandard clock architectures.
Actually this was my very first implementation, even in simulation it had to be made on boards someday keeping timing skew and capacitance of boards in mind i decided to flip the clock, this will give the control unit a head start of half a cycle and get everything ready before the clock reached the next high, this trick was also used in one of the projects I mentioned at last page in the document. I had to probe and check every signal keeping the standard gate delays of 74 series in equation too!
Not having interrupts isn't necessarily a problem. In fact if you want to be sure that the processor behaves deterministically then you might choose to not have interrupts. I remember seeing an article about the British RAF commissioning a CPU design and explicitly forbidding interrupts for that reason. Unfortunately I don't remember where I saw it so I can't check to see if my memory is faulty.
The dual phase clocking is perhaps inspired by the 6502.