The iteration cycles are limited necessarily by the time between tapeout and getting chips off the line to a testable state. Maybe there's a little room to get an in-wafer test probe system built at the fab if each die has a standard pad layout, which would speed up the 'testable state' part of that timeline. But if your timeline is weeks (if only!) to months, there's little utility in being able to make incremental changes on a daily basis.

Plus, the only way fab costs become achievable are MPW runs which don't have adequate demand for multiple daily runs. The ones I've used run a few processes each month, rotating between most of them on a bimonthly to quarterly basis. They just don't fill up fast enough. But I'm small time fabless so maybe I'm missing something.