It's a proof that something is possible to show one example.
In this case the claim was ASIC-resistant PoW is possible, and the proof has been the historical behavior of miners after years of RandomX. Nobody said it would be eternally or entirely resistant to optimizations...
You are twisting words beyon any coherent meaning.
> It's a proof that something is possible to show one example.
Agreed.
> the proof has been the historical behavior of miners after years of RandomX.
> Nobody said it would be eternally or entirely resistant to optimizations...
These are contradictory statements. If historical behavior was a proof, then it would be eternally and entirely resistant.
The limit we set at the beginning was "no one can design a custom device for RandomX with more than a 2:1 efficiency advantage over general purpose CPUs". That is and will forever remain true.
In reality, no one has been able to build any device for RandomX that isn't actually a CPU. The closest thing to a "mining ASIC" is just a bunch of RISC-V cores.