This is reasonably common - Nordic and ST do this as well on the nrf-53 and STm32WB/L respectively. It's convenient for concurrency, and separation of concerns.
This is reasonably common - Nordic and ST do this as well on the nrf-53 and STm32WB/L respectively. It's convenient for concurrency, and separation of concerns.
Espressif themselves do this for their own prerogatives. The ESP32-S3 MCU from this story actually has a small, low power RISC-V core that deals with several things, including "deep sleep" tasks. Many ESP32-S3 users are unaware that their dual core Xtensa device also includes a RISC-V core; it's just there, transparently doing Expressif stuff on a dedicated core.
Also, running the network stack on a separate core allows it to be encrypted and signed, so that end users can't (easily) reverse engineer it. Which sucks for those of us who would like to run fully open-source code without binary blobs.
For instance, compare the reference manuals for the STM32WL3R and the STM32WB microcontrollers. The former has a single CPU, and it has almost 250 pages of detailed documentation about exactly how the hardware is controlled at a register level. The latter runs the network stack on an auxiliary CPU, and the manual just has a block diagram and a sentence that says "use our drivers" (which are only available in encrypted format).