> Reverse-engineering the Pi 5's MIPI to push 5.6 Gbps from custom MASH sigma-delta ADCs to a Lattice ECP5 FPGA to the Raspberry Pi is serious engineering

Using video interfaces to transfer arbitrary data at high speeds is becoming a common trick for cheap boards with limited interfaces. Video inputs and outputs are generally highly mature and optimized to avoid dropping frames because everyone wants reliable video. Putting arbitrary data into video IO pipelines is a cheap way to get high speed IO through standard interfaces.

There is a cool project that uses cheap HDMI to USB capture devices for high speed data transfer out of cheap FPGA boards that have HDMI output [ https://github.com/steve-m/hsdaoh ]

In a perfect world, using PCIe directly would be a much better solution for a project like this. Having access to PCIe DMA support directly without relying on video IO peripherals is helpful for high speed ADC/DAC applications like this. It would also make the board more portable to other SBCs.

The ECP5-5G can do PCIe 2.0 x2 or PCIe 1.0 x4 which would provide around 8Gbps of data transfer. The problem is that the Raspberry Pi 5 only exposes a single PCIe lane to the user. The other 4 PCIe lanes of the Raspberry Pi 5 SoC are routed to the RP1 chip, which has the MIPI and CSI interfaces that are used in this project. So the data is going through a convoluted path instead of being connected to PCIe directly.

I would have to look at the details more closely, but even using the PCIe 2.0 x1 port (around 4 Gbps after overhead) on the Raspberry Pi would be close in bandwidth to the 5.6 Gbps number they give for their custom MIPI solution.

I think the Raspberry Pi 5 is a good first choice for most projects because it is widely support and has the largest community, but for a project like this the benefits of moving to a different SBC with PCIe 2.0 x2 would have been helpful. Keeping the project semi-independent of the SBC has a lot of benefits.