Nice specs! Looking forward to seeing how this and the other projects on Waferspace goes. Being able to produce 1k chips at a reasonable price will hopefully do wonders for open hardware / open silicon.
Nice specs! Looking forward to seeing how this and the other projects on Waferspace goes. Being able to produce 1k chips at a reasonable price will hopefully do wonders for open hardware / open silicon.
Yep, Aegis's Terra 1 is designed to be "good enough" for the first generation. I do plan on expanding the Terra family of FPGA's if there's enough interest. I do want to work my way up to 100k LUT's.
What are your thoughts on including a RISC-V hardcore along with the gates? Because for almost all projects I can imagine using FPGA for, I would want a microcontroller also. This might however be slightly colored by me being a software/firmware first type of electronics engineer. Thinking especially for the smaller gate counts, like under 10k - because there a soft CPU takes up very precious resources.
I've definitely had a thought about doing a hard core RISC-V SoC on a dev board.
1k chips for $4000 or $7000 at 180nm is (a lot) more expensive than 180nm at MOSIS or Europractice, I wound not call it reasonable, especially because the EDA software tools and PDK used are inferior.
I went though the list of prices at Europractice. Waferspace is 7000 USD for 1k of 20mm2. That is a per mm2 price of 350 USD. I could not find any offering at Europrice that matches that?
Chip fabs do not publish prices. First of all, the cost price of making a wafer is not a single item. What node, on what chip machine are they going to be made, what process, what PDK, are you breaking any of the PDK limits, what testing has your design went trough, what types and numbers of slices to chip the wafer, are there test before the chips get chipped or only after they are chipped, what packages the chips are in. Insurance types and fees, locations, what batches. All these steps can be performed in different fabs with different companies and subcontractors, between them they might have to ship your wafer under clean room conditions, sometimes flow around the world. A wafer batch price is a very complex multi-party negotiation under NDAs, none of them has ever been made public. Show me any credible price quotes from the last 55 year (fe few million chips). You can't.
On these multi party shuttle projects this gets simplified into a price list where they quote you a high ball-park number that covers your test chips cost by a wide margin. The actual cost is never disclosed, certainly not on price lists.
A mask set maker and a chip fab create half of your product, they own that intellectual product and they won't even tell you what it has cost them. They merge their product with yours, now thyey co-own your product. There are only a few competing companies world wide (and getting fewer every year) and they compete on all this non-disclosed stuff. Prices above all. Never belief what you read on the internet, especially in the chips war industry.
Interesting! Which EDA tool must I use for those, and what is the price of that? Will these services accept a single run of 1k?
There are a few EDA companies, all with ancient software tools but kept up to date with the changing parameters and algorithms. You use the tools the insurance companies tell you or the mandatory tools of your chip fab suppliers. They use a lot of software tools on your design files you never get to see.
If you want to make better chips, like the low power Apple Silicon for example, you create your own EDA software tools to make the innovation. Creating a new transistor like the CFET [1] means writing new physics simulation tools, for example.
The outdated 1990's and buggy Open Lane software for example limits what kind of RAM transistors you can make or the complexity of your design.
My team makes asynchronous chips, free space optics photonics, ultra dense 2 transistor SRAM, niobium SQF chips, wafer scale integrations. All require bespoke software simulation tools, netlist rewriting tools, cross-reticle stepper exposure software (a software change in a $400 million dollar machine), etc etc. Making hardware near atomic size structures is mostly a software job. Hardware is software crystalized early, Alan Kay quips.
[1] https://www.imec-int.com/en/articles/imec-puts-complementary...