Thanks, it was very instructive.
I know of DLP and I know of temporal dithering, which I lump into the "oscillatory stuff" which I assume has significant power consumption compared to the static scenarios like MIP LCD. I think I also conflate any dynamic refresh process into this same category, though I guess that may be too broad a brush...
When I was thinking about the sub-areas to implement an optical DAC, I was thinking about this in the low power realm of a self-sustaining MIP LCD without display refresh, but with more bit depth.
What I didn't fully appreciate is the nice analogy of regular active matrix LCD to DRAM. I did understand that MIP LCD sounds like embedded SRAM.
The difference with active-matrix that it is analog, right? I.e. the DAC is in the part of the display driver that is generating a pixel serialized signal that is distributed out to the panel lines and columns? So the different sub-pixel levels are analog voltages applied during this refresh, and the dynamic "memory" is some combination of the floating transistor input and the intrinsic physical hysteresis of the liquid crystal cell. (By contrast, MIP is actually holding a digital value at the sub-pixel.)
>> When I was thinking about the sub-areas to implement an optical DAC, I was thinking about this in the low power realm of a self-sustaining MIP LCD without display refresh, but with more bit depth.
Yes, this is correct. You can call it an optical DAC, a term I otherwise never heard before. :-) The summation happens in the eyes because of spatial/temporal resolution limits.
>> The difference with active-matrix that it is analog, right? I.e. the DAC is in the part of the display driver that is generating a pixel serialized signal that is distributed out to the panel lines and columns? So the different sub-pixel levels are analog voltages applied during this refresh, and the dynamic "memory" is some combination of the floating transistor input and the intrinsic physical hysteresis of the liquid crystal cell. (By contrast, MIP is actually holding a digital value at the sub-pixel.)
Yes.
Without digital memory in pixel, the DAC(s) are outside the pixel array. Could be common across the entire panel (would need very high speed then), one per column, etc.
>> What I didn't fully appreciate is the nice analogy of regular active matrix LCD to DRAM.
Guess what, the said "DRAM" can be read as well, not just written to! I have previously (nearly two decades back) designed sophisticated circuits for display / pixel calibration using this. To be clear, the purpose was not to use a display panel as memory, and nor was I able to use such methods for display-integrated touch-sensing*. My core purpose was pixel characterization, global auto-configuration of the controller electronics based on measurements of electrical-to-optical transfer curves, panel uniformity calibration, dead pixel detection, etc. In one of the projects, I was writing specific data to the display panel, but doing that and erasing it so fast that (even expert) human eyes could not see. :-)
* There likely have been advancements for this since then.