Several processors support this by effectively locking cache lines. At the low end, it allows a handful of fast interrupt routines without dedicated TCM. At the high end, it allows boot ROMs to negotiate DRAM links in software, avoiding both the catch 22 and complex hardware negotiation.
Several processors support this by effectively locking cache lines. At the low end, it allows a handful of fast interrupt routines without dedicated TCM. At the high end, it allows boot ROMs to negotiate DRAM links in software, avoiding both the catch 22 and complex hardware negotiation.
Instead of a cache you could put down an SRAM buffer, it would be more efficient than a cache and just as fast. And addressable. Interesting idea.