While this is a good general rule of thumb, this terminology has nothing to do with how these terms are formally defined.

Verification first and foremost concerns design and development stage, a formal definition would be something like "outputs of design and development step meet specified requirements for that step". For example, you could verify that a formal specification for a module actually implements imposed requirements. Especially in software this can get murky as you cover different phases with different tests/suites, e.g. unit, integration, e2e implicitly test different stages, yet are often part of the same testing run.

Validation first and foremost concerns the whole system/product and fitness for market availability.

For example you would verify that e.g. for a motor vehicle ABS functions correctly, airbags deploy in a crash and frame meets passenger safety requirements in a crash, and you would still not be able to sell such vehicle. You would validate the vehicle as a whole with corresponding regulatory body to get vehicle deemed fit for market.

TLDR: Verification is getting passing grade in a lab test, validation is submitting all relevant lab test protocols to get CE certified.