Nice! Unrelated to the other open-source SPARK for designing and deploying small, composable data processing graphs with a Python API, I guess?
Are you thinking about supporting deployment on FPGAs like the iCE40 line?
Nice! Unrelated to the other open-source SPARK for designing and deploying small, composable data processing graphs with a Python API, I guess?
Are you thinking about supporting deployment on FPGAs like the iCE40 line?
Currently FPGAs are out of scope. But, would love to implement that use case as well in future.
I've been clumsily exploring the space of what kind of DSP you can do without multipliers, because (in hardware) multiplication is one or two orders of magnitude more expensive than addition; see https://nbviewer.org/url/canonical.org/~kragen/sw/dev3/spars... for one example.
This is a fascinating space where logarithmic numbers can offer a lot of value with fewer bits.
Can they?