Sure, it’s not coded the same way as your external ISA does it (like you said, lots of wide information), but the core is optimized for a load/store architecture with ops that generally execute in a single pipeline stage, and the big, complex instructions in the ISA map to multiple smaller micro-ops. But yes, it is NOT literally an x86 decoder wrapped around a MIPS or ARM core.
No. NOT a load/store architecture. People tried that in the 90's for x86. Doesn't work nearly as well as keeping µops generally the same as the simpler move/ALU instructions of the external ISA, just encoded differently. That's what modern x86 uses, that's what modern z/Arch ("S/360-31-64++") uses.
x86 and z/Arch instructions for move/ALU/jmp/conditional branch are fine. They are not hard to decode and they are not hard to execute. That's the core of the µop instruction set (just encoded differently). Then they add some specialty stuff necessary to implement more complex instructions using sequences of µops -- and of course the SIMD stuff. That's it. It's a simpler version of the external ISA, NOT a RISC.
Part of the path the µops take is wide, possibly with the option of a shared field for a large immediate.
Instructions that map to short, fixed-length µops sequences are handled directly by the decoders that spit out a wide chunk of µops. Longer or variable-length µops are handled by having the decoders emit an index into a ROM of wide µops chunks. The decoders can often spit out both the first wide chunks AND the index (so there's no need to wait a cycle for the ROM to emit µops).
Multi-cycle µops are not much of problem, as long as the cycle count is predictable, preferably statically predictable. It is common to have µops that are "multi-issue", for example if they involve memory operands.
Hm. Maybe I’m using terms incorrectly or my model for what is happening is incorrect. Please educate me.
“NOT a load/store architecture.” What do you mean by this, exactly?
“It's a simpler version of the external ISA, NOT a RISC.” How are defining “RISC,” exactly? What makes it not a RISC given that you’re also saying it’s simpler?