This is true, but unless great care is taken to generate nice Verilog you're going to run into issues when you try to integrate standard tools like functional coverage, formal SVA, etc.
I haven't looked at the Chisel SVA but I do recall another HDL touting readable Verilog generation as a feature in response to Chisel's being bad (can't remember which one) so I guess it can't be great.
I think Veryl stands a decent chance of success precisely because it hews so closely to SystemVerilog - you don't lose access to all the feature industry uses. It's kind of the Typescript of SystemVerilog.