Yes, that's basically the relationship between CoVE and ACE, from a quick glance. In this case, ACE is simply implementing a formally modeled and verified security monitor where the design has been extracted to Coq and the invariants proven.

It can work on P550 because CoVE supports several "Deployment strategies", the one ACE uses is referenced in the README: CoVE spec, Appendix D, "M-mode [Trusted Security Manager] based deployment model" https://github.com/riscv-non-isa/riscv-ap-tee/blob/main/src/... -- the other appendicies detail e.g. Smmtt based designs, and apparently there's a not-yet-written "Nested Virtualization" design in Appendix C.

They also note that the P550 isn't a "true" port due to the preliminary, non-ratified H extension, and it also misses another required extension called "Sstc" but they just emulate it. (Sstc is interesting; it seems to be a performance optimization for delivering timer interrupts directly to supervisors, but I can imagine in the case of CoVE timer interrupts going through M-mode could leak data, making it more of a security issue.)

Leveraging M-mode is basically how previous security monitors like keystone worked too, back on the original HiFive Unleashed. It just sorta treats M-mode as an analogue to the "secure world" in ARM parlance, though there is no requirement that M-mode has e.g. an encrypted memory controller and dedicated memory region, and I'm guessing other things (I'm not super familiar with TrustZone.)

Broadly speaking this reminds me as a kind of a evolution/combination of Microsoft's Komodo (formally verified, but was only for e.g. SGX-style enclaves) and existing M-mode TEE systems like Keystone -- but upgraded to support "Confidental Computing" virtual machines. So that's quite nice.

The CoVE specification defines a unified confidential computing architecture for RISC-V that scales across embedded, edge, and cloud use cases. The system designers select the appropriate deployment model based on the specific constraints and goals of their target systems. ACE adopts the deployment model tailored for mid- to high-end embedded platforms (see Appendix D in the CoVE spec).

Ultimately, we should expect multiple CoVE implementations optimized for different domains. For instance, in cloud environments, the focus is on maximizing performance and resource utilization—typically requiring full CoVE support and advanced hardware features such as Smmtt and AIA. Salus from Rivos is an example of such a high-end implementation. In contrast, embedded systems have limited power and silicon budgets, and thus prioritize simpler hardware. These systems trade off performance and accept memory fragmentation in favor of reduced hardware complexity and cost—ACE is designed with this trade-off in mind.

ACE runs on P550 by emulating the missing hardware features. This enables experimental deployment on real hardware. (P550 is the first commercially available RISC-V processor with virtualization support.)