> In a frontside design, the silicon substrate can be as thick as 750 micrometers. Because silicon conducts heat well, this relatively bulky layer helps control hot spots by spreading heat from the transistors laterally. Adding backside technologies, however, requires thinning the substrate to about 1 mm to provide access to the transistors from the back.
This is a typo here, right? 1mm is thicker, not thinner, than 750 micrometers. I assume 1µm was meant?
I think you're right that 1µm was meant given the orders of magnitude in other sources e.g. 200µm -> 0.3µm in this white paper:
https://www.cadence.com/en_US/home/resources/white-papers/th...
Wafers on some semiconductor processes are 0.3m in diameter. You could not practically handle a 1um thick wafer 0.3m in diameter without shattering it. 0.75mm is a reasonable overall wafer thickness.